Semiconductor integrated circuit device and production method thereof

ABSTRACT

A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.  
     Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor integratedcircuit device and a technique for manufacturing the semiconductorintegrated circuit device. More particularly, the present inventionrelates to a technique effectively applied to a semiconductor integratedcircuit device having: a highly integrated memory circuit using a spacermade of a silicon oxide film and a silicon film; and a logic embeddedmemory in which a memory circuit and a logic circuit are provided on thesame semiconductor substrate, and applied to a production methodthereof.

[0002] In the conventional logic embedded memory in which the DRAM(Dynamic Random Access Memory) and the logic circuit are provided on thesame semiconductor substrate, a type polycrystalline silicon film whosea conductivity type is an n type has been used for the gate electrode ofan n channel MISFET (Metal Insulator Semiconductor Field EffectTransistor).

[0003] However, in order to improve the operation speed of the entireDRAM and continue to store data in a memory cell, the research andcircuit design about various structures and circuit designs have beenperformed because of an improvement of a so-called refreshcharacteristic, that is, a characteristic of refreshing regularly thememory contents thereof.

[0004] Also, there has been the problem of enhancing the thresholdvoltage of a memory cell selecting MISFET in the memory cell. As thespecific solution thereof, for example, Japanese Patent Laid-open No.2000-174225 has disclosed that a polycrystalline silicon whose aconductivity type is a P type is used for gate electrodes of an nchannel memory cell selecting MISFET and a p channel MISFET constitutingthe peripheral circuit of the DRAM.

SUMMARY OF THE INVENTION

[0005] In the conventional technique described above in which thepolycrystalline silicon whose the conductivity type is a p type is usedfor the gate electrode, no consideration has been made to an increase inboron penetration through a gate oxide, due to the silicon nitride filmused in a gate electrode structure. Therefore, there have been problemsof the variance of a threshold voltage and the degradation of a blockingvoltage due to the boron penetrated through the gate oxide.

[0006] An object of the present invention is to provide a techniquecapable of improving the refresh characteristic in the semiconductorintegrated circuit device having the DRAM and the logic embedded memory.

[0007] Another object of the present invention is to provide a techniquecapable of improving the driving capability of the MISFET in the logiccircuit, in the semiconductor integrated circuit device having the DRAMand the logic embedded memory.

[0008] The above and other objects and novel features of the presentinvention will be apparent from the descriptions of this specificationand the accompanying drawings.

[0009] The p type polycrystalline silicon gate electrode having a largework function is used as the gate electrode of the memory cell selectingn channel MISFET. As a result, the introduction of the impurity for theadjustment of the threshold voltage becomes unnecessary, and thesubstrate concentration can be reduced. Also, since the electric fieldnear the junction of the semiconductor area to which a capacitor isconnected is decreased, the leakage current between the storage node andthe semiconductor substrate is decreased. Therefore, it is possible toimprove the refresh characteristic thereof.

[0010] Also, a film containing no hydrogen or little hydrogen, such as asilicon oxide film, is used as the insulating film on the upper portionof the gate electrode and as the first film on the sidewall of the gateelectrode. As a result, the accumulation amounts of not only hydrogenbut also ammonia that promote the boron penetration are reduced, andfurther the emission amounts of these can be reduced. Therefore, thevariance of the threshold voltage and the degradation of the gateblocking voltage can be reduced.

[0011] In addition, a conductive film is deposited on the gate electrodeand between the gate electrode and a gate electrode adjacent thereto, bythe use of the first film on the sidewall of the gate electrode, and theconductive film on the gate electrodes is polished (CMP) until the firstfilm is exposed, and thereby a contact electrode is formed. As a result,it is possible to form the contact electrode in a self-alignment manner.

[0012] Also, the first and second films are left on the sidewalls of thegate electrodes of the n channel MISFET and the p channel MISFET thatare formed in the peripheral circuit forming area, and are used as amask to implant impurities into both sides of each of the gateelectrodes of the n channel MISFET and the p channel MISFET and therebyform the semiconductor area. As a result, the sidewall spacer on thesidewall of the gate electrode in the peripheral circuit forming areacan be formed more thickly than that in the memory cell area. Therefore,it is possible to achieve the downsizing of the n channel MISFET and thep channel MISFET that constitute the logic circuit and the improvementof the reliability thereof.

[0013] Also, if a p type impurity such as boron or the like is implantedby the ion implantation, the p type polycrystalline silicon gateelectrode having a desirable impurity concentration can be formed.Further, if the p type polycrystalline silicon gate electrode is used inthe p channel MISFET formed in the peripheral circuit forming area, thechannel thereof is a surface type. Therefore, the downsizing of the pchannel MISFET is facilitated and the performance of the p channelMISFET can be improved.

[0014] Also, since the lower electrode and the upper electrode of thecapacitor constituting the memory cell are made of metal (so-called MIMstructure), it is possible to decrease the annealing temperaturerequired at the time of forming the capacitor to 600° C. or lower, andthus prevent the boron penetration.

[0015] In addition, since the open bit line arrangement is employed inthe memory cell, it is possible to make the memory cell highlyintegrated.

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0016]FIG. 1 is a cross-sectional view showing the principal part of asemiconductor integrated circuit device according to a first embodimentof the present invention.

[0017]FIG. 2 is a cross-sectional view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0018]FIG. 3 is a plan view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0019]FIG. 4 is a cross-sectional view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0020]FIG. 5 is a cross-sectional view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0021]FIG. 6 is a cross-sectional view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0022]FIG. 7 is a cross-sectional view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0023]FIG. 8 is a cross-sectional view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0024]FIG. 9 is a cross-sectional view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0025]FIG. 10 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0026]FIG. 11 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0027]FIG. 12 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0028]FIG. 13 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0029]FIG. 14 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0030]FIG. 15 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0031]FIG. 16 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0032]FIG. 17 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0033]FIG. 18 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0034]FIG. 19 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0035]FIG. 20 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0036]FIG. 21 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0037]FIG. 22 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0038]FIG. 23 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0039]FIG. 24 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0040]FIG. 25 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0041]FIG. 26 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0042]FIG. 27 is a plan view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess.

[0043]FIG. 28 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0044]FIG. 29 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0045]FIG. 30 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0046]FIG. 31 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0047]FIG. 32 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device of FIG. 1 during theproduction process.

[0048]FIG. 33 is a cross-sectional view showing the principal part of asemiconductor integrated circuit device according to a second embodimentduring the production process thereof.

[0049]FIG. 34 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0050]FIG. 35 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0051]FIG. 36 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0052]FIG. 37 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0053]FIG. 38 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0054]FIG. 39 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0055]FIG. 40 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0056]FIG. 41 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0057]FIG. 42 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the secondembodiment during the production process thereof.

[0058]FIG. 43 is a cross-sectional view showing the principal part of asemiconductor integrated circuit device according to a third embodimentduring the production process thereof.

[0059]FIG. 44 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the thirdembodiment during the production process thereof.

[0060]FIG. 45 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the thirdembodiment during the production process thereof.

[0061]FIG. 46 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the thirdembodiment during the production process thereof.

[0062]FIG. 47 is a cross-sectional view showing the principal part of asemiconductor integrated circuit device according to a fourth embodimentduring the production process thereof.

[0063]FIG. 48 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the fourthembodiment during the production process thereof.

[0064]FIG. 49 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the fourthembodiment during the production process thereof.

[0065]FIG. 50 is a cross-sectional view showing the principal part ofthe semiconductor integrated circuit device according to the fourthembodiment during the production process thereof.

[0066]FIG. 51 is a plan view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess thereof.

[0067]FIG. 52 is a plan view showing the principal part of thesemiconductor integrated circuit device of FIG. 1 during the productionprocess thereof.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

[0068] (First Embodiment)

[0069] Hereinafter, embodiments of the present invention will bedescribed in detail based on the drawings.

[0070]FIG. 1 is a cross-sectional view showing the principal part of asemiconductor integrated circuit device according to a first embodimentof the present invention. FIGS. 2 to 32 are cross-sectional views andplan views showing the principal part of the semiconductor integratedcircuit device of FIG. 1 during the production process thereof.

[0071] First, the sectional structure of a semiconductor integratedcircuit device according to the first embodiment will be described withreference to FIG. 1.

[0072] A semiconductor substrate 1 is made of, for example, a singlecrystal silicon whose a conductivity type is a p type. Thissemiconductor substrate 1 has a memory cell area and logic circuit areas(peripheral circuit area), and the central portion of FIG. 1 illustratesthe memory cell area and the left side of the memory cell areaillustrates a first logic circuit area and the right side of the memorycell area illustrates a second logic circuit area.

[0073] A deep n well 2 n is formed in the semiconductor substrate 1 inthe memory cell area. For example, an n type impurity such as phosphorusis introduced into this deep n well 2 n.

[0074] A p well 3 pm is formed in an upper layer of this deep n well 2n. The periphery of this p well 3 pm is surrounded by the deep n well 2n and n wells 3 n, and is electrically isolated from the first andsecond logic circuit areas and the like. For example, a p type impuritysuch as boron is introduced into this p well 3 pm. The concentration ofthe p type impurity is, for example, within a range of about 10¹⁷ to10¹⁸/cm³.

[0075] Also, a p well 3 p is formed in each of the first and secondlogic circuit areas of the semiconductor substrate 1. For example, a ptype impurity such as boron is introduced into each p well 3 p. Theconcentration of the p type impurity is, for example, within a range ofabout 10¹⁷ to 10¹⁸/cm³. The p well 3 p is almost as deep as the p well 3pm in the memory cell area.

[0076] Further, an n well 3 n is formed in each of the first and secondlogic circuit areas of the semiconductor substrate 1. For example, an ntype impurity such as phosphorus or arsenic (As) is introduced into then well 3 n. The concentration of the n type impurity is, for example,within a range of about 10¹⁷ to 10¹⁸/cm³. The n well 3 n is almost asdeep as the p well 3 pm in the memory cell area.

[0077] Isolation areas are provided between the memory cell area and thefirst and second logic circuit areas and between the memory cell areaand the second logic circuit area, respectively. An isolation trenchhaving a depth of 0.3 to 0.4 μm in a thickness direction of thesemiconductor substrate 1 is formed in each of the isolation areas, andan insulating film 4 for isolation is buried inside each isolationtrench. Also, the isolation areas are provided between the p well 3 pand the n well 3 n in the first and second logic circuit areas,respectively.

[0078] This insulating film 4 for isolation is made of, for example,silicon oxide (SiO₂) or the like. Note that the upper surface of theinsulating film 4 for isolation is flattened so as to be almost as highas the main surface of the semiconductor substrate 1.

[0079] A memory cell of the DRAM is formed in the memory cell area ofthe semiconductor substrate 1 (on the p well 3 pm). This memory cell iscomposed of a memory cell selecting MISFET Q and a capacitor (capacitorfor information storage) C.

[0080] The memory cell selecting MISFET Q has a pair of semiconductorareas 5 a and 5 b formed apart from each other on the p well 3 pm, agate insulating film 5 i formed on the semiconductor substrate 1, and agate electrode 5 g formed thereon. Note that the threshold voltage ofthe memory cell selecting MISFET Q is, for example, about 1V.

[0081] The semiconductor areas 5 a and 5 b are areas functioning as thesource and drain of the memory cell selecting MISFET Q, and an n typeimpurity such as phosphorus or As is introduced into these areas. Achannel area of the memory cell selecting MISFET Q is formed between thesemiconductor areas 5 a and 5 b (immediately below the gate electrode 5g).

[0082] In addition, the gate electrode 5 g has a so-celled poly-metalgate structure formed by sequentially depositing, for example, alow-resistance polycrystalline silicon film, a tungsten nitride (WN)film (not shown), and a tungsten film from below. This poly-metal gatestructure makes it possible to reduce a sheet resistance to about 2 Ω/□,and thereby it is possible to achieve a low resistance of the gateelectrode. Thus, the operation speed of the DRAM can be improved. Thepoly-metal gate structure like this can be employed as materials of notonly a gate electrode but also a wiring. This gate electrode 5 g has afunction as a word line of the memory cell.

[0083] A p type impurity such as boron is introduced into thislow-resistance polycrystalline silicon film constituting this gateelectrode 5 g. Thus, advantages as follows can be obtained.

[0084] That is, even if the impurity concentration of the semiconductorsubstrate 1 (namely, an impurity concentration of the p well 3 mp;referred to as substrate concentration hereinafter) is not increased,the threshold voltage of the memory cell selecting MISFET Q can beincreased.

[0085] The reason thereof is as follows. That is, since the workfunction of the p type polycrystalline silicon is about 5.15V which islarger than 4.15V of the n type polycrystalline silicon by about 1V, then channel memory cell selecting MISFET Q using a gate electrode made ofp type polycrystalline silicon can have a threshold voltage higher byabout 1V than the n channel memory cell selecting MISFET using a gateelectrode made of n type polycrystalline silicon even in the case wherethe substrate concentrations of the MISFETs are equal to each other.

[0086] Therefore, it is unnecessary to introduce impurities (foradjustment of the threshold voltage) for increasing the threshold value,into the channel area immediately below the gate electrode 5 g, and thusit is possible to reduce the substrate concentration.

[0087] The reduction in the substrate concentration as described abovemakes it possible to decrease an electric field near a junction of thesemiconductor area 5 a to which the capacitor C is connected. Therefore,it is possible to reduce the leakage current between a storage node(capacitor C) and the semiconductor substrate 1. The reduction of theleakage current makes it possible to improve the refresh characteristicof the memory cell.

[0088] A gate insulating film 5 i is made of, for example, silicon oxideand the thickness thereof is set, for example, to be about 6 nm.

[0089] A cap insulating film 6 made of, for example, silicon oxide isformed on the upper surface of the gate electrode 5 g of the memory cellselecting MISFET Q. Also, a sidewall film 7 made of, for example,silicon oxide is formed on the side surface of the gate electrode 5 g.By doing so, it is possible to achieve the prevention of the boronpenetration through the gate electrode of the p type polycrystallinesilicon.

[0090] More specifically, in the case where a film made of siliconnitride is utilized on an upper surface or a side surface of the gateelectrode 5 g (word line) or on a surface of the substrate, sincehydrogen and ammonia used as materials thereof are accumulated in thefilm, these hydrogen and ammonia promote the penetration of boronthrough the substrate.

[0091] However, since the silicon nitride film is not used in thisembodiment, the penetration of boron from the gate electrode of p typepolycrystalline silicon can be reduced.

[0092] Meanwhile, an n channel MISFET Qn is formed in the first logiccircuit area (on the p well 3 p) shown in the left side of FIG. 1. The nchannel MISFET Qn has semiconductor areas 8a1 and 8a2 formed apart fromeach other on the upper portion of the p well 3 p, a gate insulatingfilm 8 i formed on the semiconductor substrate 1, and a gate electrode 8f formed thereon. Note that the threshold voltage of the MISFET Qn is,for example, about 0.1V

[0093] The semiconductor areas 8a1 and 8a2 function as the source anddrain of the n channel MISFET Qn, and the channel area of the n channelMISFET Qn is formed between the semiconductor areas 8a1 and 8a2(immediately below the gate electrode 8 g).

[0094] These semiconductor areas 8a1 and 8a2 have an LDD (Lightly DopedDrain) structure. More specifically, each of the semiconductor areas 8a1and 8a2 has a low concentration area 8 c and a high concentration area 8e. This low concentration area 8 c extends in the direction opposite tothe channel area from an end portion of the gate electrode 5 g, and thehigh concentration area 8 e extends in the same direction as that of thelow concentration area 8 c from a position a little apart from the endportion of the gate electrode 5 g.

[0095] N type impurities such as As and phosphorus are introduced intothe low concentration area 8 c. Although n type impurities such as Asand phosphorus are introduced also in the high concentration area 8 e,the impurity concentration thereof is set higher than that of the lowconcentration area 8 c.

[0096] In addition, the gate electrode 8 f has a so-celled poly-metalgate structure formed by sequentially depositing, for example, alow-resistance polycrystalline silicon film, a tungsten nitride (WN)film (not shown), and a tungsten film from below. This poly-metal gatestructure makes it possible to reduce the sheet resistance to about 2Ω/□, and thereby it becomes possible to achieve a low resistance of thegate electrode. Thus, the operation speed of a logic circuitconstituting the peripheral circuit of the DRAM can be improved.

[0097] A cap insulating film 6 made of, for example, silicon oxide(SiO₂) is formed on the upper surface of the gate electrode 8 f. Also, asidewall film 7 made of, for example, silicon oxide is formed on theside surface of the gate electrode 8 f.

[0098] The gate insulating film 8 i is made of, for example, siliconoxide and the thickness thereof is designed to be about 3.5 nm.

[0099] A p channel MISFET Qp is formed on the n well 3 n in the firstlogic circuit area shown in the left side of FIG. 1. The p channelMISFET Qp has a pair of semiconductor areas 9a1 and 9a2 formed apartfrom each other on the n well 3 n, a gate insulating film 9 i formed onthe semiconductor substrate 1, and a gate electrode 9 f formed thereon.Note that the threshold voltage of the MISFET Qp is, for example, about−0.1V.

[0100] The semiconductor areas 9a1 and 9a2 function as the source anddrain of the p channel MISFET Qp, and the channel area for the p channelMISFET Qp is formed between the semiconductor areas 9a1 and 9a2(immediately below the gate electrode 9 f).

[0101] The semiconductor areas 9a1 and 9a2 have the LDD structure. Morespecifically, each of the semiconductor areas 9a1 and 9a2 has a lowconcentration area 9 c and a high concentration area 9 e. This lowconcentration area 9 c extends in a direction opposite to the channelarea from an end portion of the gate electrode 5 f, and the highconcentration area 9 e extends in the same direction as the lowconcentration area 9 c, from the position spaced a predetermineddistance away from the end portion of the gate electrode 5 f.

[0102] A p type impurity such as BF₂ is introduced into the lowconcentration area 9 c. Although a p type impurity such as boron or BF₂is introduced also into the high concentration area 9 e, the impurityconcentration thereof is set higher than that of the low concentrationarea 9 c.

[0103] The gate electrode 9 f has a so-celled poly-metal gate structureformed by sequentially depositing, for example, a low-resistancepolycrystalline silicon film, a tungsten nitride (WN) film (not shown),and a tungsten film from below. This poly-metal gate structure makes itpossible to reduce the sheet resistance to about 2 Ω/□, and thereby itis possible to achieve a low resistance of the gate electrode. Thus, theoperation speed of a logic circuit constituting the peripheral circuitof the DRAM can be improved.

[0104] Also, the p type impurity such as boron or BF₂ is introduced intothe low-resistance polycrystalline silicon film of the gate electrode 9f. By setting the gate electrode of the p channel MISFET Qp at a p type,it is possible to reduce the threshold voltage of the p channel MISFETQp, and consequently adapt the low voltage operation. In this manner,the improvement in the characteristic and the operation reliabilitythereof is achieved.

[0105] The gate insulating film 9 i is made of, for example, siliconoxide and the thickness thereof is designed to be about 3.5 nm.

[0106] The cap insulating film 6 made of, for example, silicon oxide isformed on the upper surface of the gate electrode 9 f. Also, thesidewall film 7 made of, for example, silicon oxide is formed on theside surface of the gate electrode 5 g. These films can prevent theboron penetration through the gate electrode made of the p typepolycrystalline silicon. More specifically, as described above, sincethe silicon nitride film containing hydrogen and ammonia that promotethe boron penetration through the substrate is not used, the boronpenetration from the gate electrode made of the p type polycrystallinesilicon can be reduced.

[0107] Note that the n channel MISFET Qn and the p channel MISFET Qpconstitute the logic circuits of the DRAM, such as a sense amplifiercircuit, a column decoder circuit, a column driver circuit, a rowdecoder circuit, an I/O selector circuit, and the like.

[0108] Meanwhile, an n channel MISFET QN is formed in the second logiccircuit area (on the p well 3 p) shown in the right side of FIG. 1. Then channel MISFET QN has a pair of semiconductor areas 8b1 and 8b2 formedapart from each other on the p well 3 p, a gate insulating film 8 jformed on the semiconductor substrate 1, and a gate electrode 8 g formedthereon. Note that the threshold voltage of the MISFET QN is, forexample, about 0.3 V.

[0109] The semiconductor areas 8b1 and 8b2 function as the source anddrain of the n channel MISFET QN, and the channel area of the n channelMISFET QN is formed between the semiconductor areas 8b1 and 8b2(immediately below the gate electrode 8 g).

[0110] The semiconductor areas 8b1 and 8b2 have the LDD structure. Morespecifically, each of the semiconductor areas 8b1 and 8b2 has a lowconcentration area 8 d and a high concentration area 8 e. This lowconcentration area 8 d extends in a direction opposite to the channelarea from an end portion of the gate electrode 8 g, and the highconcentration area 8 e extends in the same direction as the lowconcentration area 8 d, from a position spaced a predetermined distanceaway from the end portion of the gate electrode 8 g.

[0111] The n type impurity such as phosphorus is introduced into the lowconcentration area 8 d. In this manner, it is possible to decrease theelectric field in the vicinity of the source-drain junction of the nchannel MISFET QN capable of adapting the high voltage operation, andthus the improvement in the characteristic and the operation reliabilitythereof is achieved.

[0112] Although the n type impurities such as As and phosphorus areintroduced in the high concentration area 8 e, the impurityconcentration thereof is set higher than that of the low concentrationarea 8 d.

[0113] In addition, the gate electrode 8 g has a so-celled poly-metalgate structure formed by sequentially depositing, for example, alow-resistance polycrystalline silicon film, a tungsten nitride (WN)film (not shown), and a tungsten film from below. This poly-metal gatestructure makes it possible to reduce the sheet resistance to about 2Ω/□, and thereby achieve a low resistance of the gate electrode. Thus,the operation speed of the logic circuit constituting the peripheralcircuit of the DRAM can be improved. Also, the n type impurity such asphosphorus or As is introduced into the low-resistance polycrystallinesilicon film of the gate electrode 8 g.

[0114] The cap insulating film 6 made of, for example, silicon oxide isformed on the upper surface of the gate electrode 8 g. Also, thesidewall film 7 made of, for example, silicon oxide is formed on thesidewall of the gate electrode 8 g.

[0115] The gate insulating film 8 j is made of, for example, siliconoxide, and, similarly to the gate insulating film 5 i of the memory cellselecting MISFET Q, the thickness thereof is designed to be, forexample, about 6 nm.

[0116] Also, a p channel MISFET QP is formed in the second logic circuitarea shown in the right side of FIG. 1. The p channel MISFET QP has apair of semiconductor areas 9b1 and 9b2 formed apart from each other onthe n well 3 n, a gate insulating film 9 j formed on the semiconductorsubstrate 1, and a gate electrode 9 g formed thereon. Note that thethreshold voltage of the MISFET QP is, for example, about −0.3 V.

[0117] The semiconductor areas 9b1 and 9b2 function as the source anddrain of the p channel MISFET QP, and the channel area of the n channelMISFET QP is formed between the semiconductor areas 9b1 and 9b2(immediately below the gate electrode 9 g).

[0118] The semiconductor areas 9b1 and 9b2 have the LDD structure. Morespecifically, each of the semiconductor areas 9b1 and 9b2 has a lowconcentration area 9 d and a high concentration area 9 e. The lowconcentration area 9 d is formed near the channel area and the highconcentration area 9 e is arranged outside the low concentration area 9d.

[0119] The p type impurity such as BF₂ is introduced into the lowconcentration area 9 d. Although the p type impurities such as boron andBF₂ are introduced also into the high concentration area 9 e, theimpurity concentration thereof is set higher than that of the lowconcentration area 9 d.

[0120] The gate electrode 9 g has a so-celled poly-metal gate structureformed by sequentially depositing, for example, a low-resistancepolycrystalline silicon film, a tungsten nitride (WN) film (not shown),and a tungsten film from below. This poly-metal gate structure makes itpossible to reduce the sheet resistance to about 2 Ω/□, and thereby itis possible to achieve a low resistance of the gate electrode. Thus, theoperation speed of a logic circuit constituting the peripheral circuitof the DRAM can be improved.

[0121] Also, the p type impurity such as boron is introduced into thelow-resistance polycrystalline silicon film of the gate electrode 9 g.By setting, at a p type, the gate electrode of the p channel MISFET QP,it is possible to reduce the threshold voltage of the p channel MISFETQP. As a result, it is possible to adapt the low voltage operation. Inthis manner, the improvement in the characteristic and the operationreliability thereof is achieved.

[0122] The gate insulating film 9 j is made of, for example, siliconoxide, and, similarly to the gate insulating film 5 i of the memory cellselecting MISFET Q, the thickness thereof is designed to be, forexample, about 6 nm.

[0123] The cap insulating film 6 made of, for example, a silicon oxidefilm or the like is formed on the upper surface of the gate electrode 9g. Also, the sidewall film 7 made of, for example, a silicon oxide filmor the like is formed on the side surface of the gate electrode 9 g. Inthis manner, the boron penetration from the gate electrode made of ptype polycrystalline silicon can be prevented. More specifically, asdescribed above, since the silicon nitride film containing hydrogen andammonia that promote the penetration of boron through the substrate isnot used, the boron penetration from the gate electrode made of the ptype polycrystalline silicon can be reduced.

[0124] Note that these n channel MISFET QN and p channel MISFET QPmentioned above constitute the logic circuits of the DRAM such as a worddriver circuit, a data input buffer circuit, a data output buffercircuit, a power supply circuit, and the like.

[0125] An interlayer insulating film 10 a fills the spaces between thesemiconductor elements such as the memory cell selecting MISFET Q, pchannel MISFETs Qp and QP, the n channel MISFETs Qn and QN, and thelike.

[0126] The interlayer insulating film 10 a is made of, for example, asilicon oxide film, and the upper surface of the interlayer insulatingfilm 10 a is formed so as to be almost as high as the respective uppersurfaces of the memory cell area and the first and second logic circuitareas.

[0127] However, contact electrodes 12 aand 12 b are formed on thesemiconductor areas 5 a and 5 b in the memory cell area, respectively.The dimensions of the contact electrodes 12 a and 12 b relative to awidth direction of the gate electrode 5 g (word line WL) are defined bythe parts of the sidewall films 7 positioned on the side surfaces of thegate electrodes 5 g adjacent to each other. More specifically, the widthdimension of each contact electrode is a distance obtained bysubtracting double of the film thickness of the sidewall film 7 from thedistance between the adjacent gate electrodes 5 g. Also, the dimensionsof the contact electrodes 12 a and 12 b relative to a height directionare defined by the height of the gate electrode 5 g. More specifically,though described later in detail, the contact electrodes 12 a and 12 bare formed in a self-alignment manner between the adjacent gateelectrodes 5 g. The contact electrodes 12 a and 12 b are made of, forexample, a low-resistance polycrystalline silicon film containing an ntype impurity such as phosphorus, and are electrically connected to thesemiconductor areas 5 a and 5 b of the memory cell selecting MISFET Q,respectively.

[0128] An interlayer insulating film 11 a is deposited on the interlayerinsulating film 10 a. The interlayer insulating film 11 a is made of,for example, a silicon nitride film and is formed by, for example, theplasma CVD (Chemical Vapor Deposition) method or the like.

[0129] An interlayer insulating film 10 b is deposited on the interlayerinsulating film 11 a. The interlayer insulating film 10 b is made of,for example, a silicon oxide film, and is formed by, for example, theplasma CVD method or the like. A (bit line) contact electrode 13 isformed in the interlayer insulating film 10 b.

[0130] An interlayer insulating film 11 b is deposited on the interlayerinsulating film 10 b. The interlayer insulating film 11 b is made of,for example, a silicon nitride film, and is formed by, for example, theplasma CVD method or the like.

[0131] An interlayer insulating film 10 c is deposited on the interlayerinsulating film 11 b. The interlayer insulating film 10 c is made of,for example, a silicon oxide film, and is formed by, for example, theplasma CVD method or the like. A bit line BL and first-layer wirings 14a and 14 b are formed in each of the interlayer insulating films 10 cand 11 b.

[0132] This bit line BL is composed of: a barrier metal film formed bysequentially depositing a titanium film and a titanium nitride film frombelow; and a tungsten film formed thereon. The bit line BL iselectrically connected to the contact electrode 12 b through the (bitline) contact electrode 13 formed in the interlayer insulating films 11a and 10 b. Further, the bit line BL is electrically connected to thesemiconductor area 5 b of the memory cell selecting MISFET Q through thecontact electrode 12 b.

[0133] Meanwhile, similar to the bit line BL, the first-layer wirings 14a and 14 b in the first and second logic circuit areas are composed of:a barrier metal film formed by sequentially depositing a titanium filmand a titanium nitride film from below; and a tungsten film formedthereon.

[0134] In this case, the first-layer wiring 14 a is electricallyconnected to the semiconductor area 8a2 of the n channel MISFET Qn andthe semiconductor area 9a1 of the p channel MISFET Qp through eachcontact electrode 15 formed in the interlayer insulating films 10 a, 11a, and 10 b and the like.

[0135] Also, the first-layer wiring 14 b is electrically connected tothe semiconductor area 8b2 of the n channel MISFET QN and thesemiconductor area 9b1 of the p channel MISFET QP through each contactelectrode 15 formed in the interlayer insulating films 10 a, 11 a, and10 b and the like.

[0136] Also, a first-layer wiring (not shown) is electrically connectedto all of the semiconductor area 8a1 of the n channel MISFET Qn, thesemiconductor area 9a2 of the p channel MISFET QP, the semiconductorarea 8b1 of the n channel MISFET QN, and the semiconductor area 9b2 ofthe p channel MISFET QP, through contact electrodes (not shown) formedin the interlayer insulating films 10 a, 11 a, and 10 b and the like.

[0137] The upper surface of the interlayer insulating film 10 c isflatly formed so as to be almost as high as all of the memory cell areaand the first and second logic circuit areas.

[0138] An interlayer insulating film 11 c is deposited on the interlayerinsulating film 10 c. The interlayer insulating film 11 c is made of,for example, silicon nitride.

[0139] A connection hole for exposing the upper surface of the contactelectrode 12 a is formed in the interlayer insulating films 11 a, 10 b,11 b, 10 c and 11 c in the memory cell area.

[0140] A contact electrode 12 c is formed in the connection hole.Further, an oxidation barrier film 16 is buried in the upper portion ofthe contact electrode 12 c. The contact electrode 12 c is made of, forexample, a low-resistance polycrystalline silicon film containing an ntype impurity such as phosphorus, and is electrically connected to thecontact electrode 12 a. Further, the contact electrode 12 c iselectrically connected to the semiconductor area 5 a of the memory cellselecting MISFET Q through the contact electrode 12 a. Also, theoxidation barrier film 16 formed in the upper portion of the contactelectrode 12 c is made of, for example, tantalum nitride.

[0141] A capacitor C is formed in a trench of a thick interlayerinsulating film 10 d formed on, for example, the interlayer insulatingfilm 11 c. The capacitor C is composed of a storage electrode 17 a, acapacitor insulating film 17 b coated on the surface of the storageelectrode 17 a, and plate electrodes 17 c, 17 d, and 17 e sequentiallycoated on the surface of the capacitor insulating film 17 b.

[0142] The interlayer insulating film 10 d is formed of, for example,silicon oxide. The storage electrode 17 a of the capacitor C is made of,for example, ruthenium. The lower portion of the storage electrode 17 ais electrically connected to the oxidation barrier film 16, and iselectrically connected to the semiconductor area 5 a of the memory cellselecting MISFET Q through the oxidation barrier film 16.

[0143] The capacitor insulating film 17 b of the capacitor C is made of,for example, tantalum oxide (Ta₂O₅) or the like. The plate electrode 17c of the capacitor C is made of, for example, ruthenium or the like, andis formed so as to cover a plurality of storage electrodes 17 a. Inaddition, both of the plate electrode 17 d made of, for example, a TiNfilm and the plate electrode 17 e made of, for example, a tungsten filmare deposited on the plate electrode 17 c.

[0144] An interlayer insulating film 10 e is deposited on the interlayerinsulating film 10 d, and thereby the plate electrodes 17 c, 17 d and 17e are coated. The interlayer insulating film 10 e is made of, forexample, a silicon oxide film or the like, and second-layer wirings 18 aand 18 b are formed on the upper surface thereof.

[0145] Each of the second-layer wirings 18 a and 18 b is formed bysequentially depositing, for example, a titanium nitride film, analuminum (Al) film, and a titanium film from below. The second-layerwirings 18 a in the first and second logic circuit areas areelectrically connected to the first-layer wirings 14 a and 14 b,respectively, through conductor films 19 in connection holes formed inthe interlayer insulating films 11 c, 10 d, and 10 e. Each conductorfilm 19 is formed by sequentially depositing, for example, a barriermetal film and a tungsten film from below. The second-layer wiring 18 bin the memory cell area is electrically connected to the plate electrode17 e through another conductor film 19 in a connection hole formed inthe interlayer insulating film 10 e. Another conductor film 19 is formedby sequentially depositing, for example, a barrier metal film and atungsten film from below.

[0146] An interlayer insulating film 10 f is deposited on the interlayerinsulating film 10 e, and thereby the second-layer wirings 18 a and 18 bare coated. The interlayer insulating film 10 f on the second-layerwiring is made of, for example, silicon oxide or the like, and is formedby, for example, the high-density plasma CVD method or the like. Thehigh-density plasma CVD method makes it possible to bury silicon oxidewith high accuracy between the second-layer wirings without voids(vacancy).

[0147] An interlayer insulating film 10 g is deposited on the interlayerinsulating film 10 f. The interlayer insulating film 10 g is made of,for example, a silicon oxide film or the like, and is formed by, forexample, the plasma CVD method or the like. The upper surfaces of theinterlayer insulating film 10 g and 10 f are flatly formed so as to havealmost the same height on the second-layer wiring and on the spacesbetween the second-layer wirings. An interlayer insulating film 10 h isdeposited on the interlayer insulating films 10 g and 10 f. Theinterlayer insulating film 10 h is made of, for example, a silicon oxidefilm or the like.

[0148] A third-layer wiring 20 is formed on the interlayer insulatingfilm 10 h. The third-layer wiring 20 is formed by sequentiallydepositing, for example, a TiN film, an Al film, and a Ti film frombelow.

[0149] The third-layer wiring 20 is electrically connected to thesecond-layer wiring 18 a through a conductor film 21 in a connectionhole formed in the interlayer insulating films 10 f, 10 g, and 10 h. Theconductor film 21 is formed by sequentially depositing a TiN film and atungsten film from below.

[0150] A passivation film composed of, for example, an insulating filmformed by laminating a silicon oxide film and a silicon nitride film isformed on the third-layer wirings 20. However, illustrations thereofwill be omitted.

[0151] Hereinafter, embodiments of the present invention will bedescribed in detail based on the production process thereof. Note thatcomponents having the same function are denoted by the same referencesymbols throughout all the drawings in order to describe theembodiments, and the repetitive descriptions thereof will be omitted.

[0152] First of all, a semiconductor substrate 1 made of, for example, ptype single crystal silicon is prepared and then MISFETs used in amemory cell and a logic circuit are fabricated. For its fabrication,element isolations for isolating MISFETs are first formed in a surfaceof the semiconductor substrate 1 by using the selective oxidation methodor the shallow trench isolation method known well.

[0153] The element isolations are formed by the shallow trench isolationmethod as follows. First, isolation trenches each having a depth ofabout 0.3 to 0.4 μm are formed in the semiconductor substrate 1 by theknown dry-etching method. Subsequently, damages to the sidewall and thebottom surface of each trench due to the dry etching are removed byforming a thin silicon oxide film (not shown) on the sidewall and thebottom surface of each trench. Next, on the substrate 1 along with theinside of each isolation trench, a silicon oxide film is deposited to afilm thickness of about 0.6 μm by the known CVD method. The siliconoxide film deposited outside each trench is selectively polished by theknown CMP (Chemical Mechanical Polishing) method, and thereby only thesilicon oxide film deposited inside the each isolation trench is left(FIG. 2). As shown in the figures, the areas between the respectiveelement isolations are set as the first logic circuit area, the memorycell area, and the second logic circuit area, in this order from theleft. FIG. 3 is a plan view showing the principal part of thesemiconductor substrate after the element isolation (silicon oxide film4) is formed in the memory cell area of the three areas. The referencenumeral 4 a in FIG. 3 denotes an element isolation area in which thesilicon oxide film 4 is buried, and the reference numeral 1 a denotes anelement forming area partitioned in the element isolation area 4 a. Theelement forming area 1 a is aslant formed relative to such a directionthat the later-described bit line BL extends. Such a layout is employedin a so-called open bit line arrangement. Note that, in this embodiment,the element forming area 1 a is formed as a slant pattern for the openbit line arrangement, but may of course be formed as other patterns fora so-called folded bit line arrangement or the like.

[0154] After a pre-oxidation treatment of the semiconductor substrate 1is performed and a photoresist film (not shown and referred to as resistfilm hereinafter) in which the memory cell area of the semiconductorsubstrate 1 is exposed is formed, an n type impurity such as phosphorusor the like is ion-implanted into the memory cell area of thesemiconductor substrate 1 with using the resist film as a mask.

[0155] Next, after a removal of the resist film, a resist film (notshown) in which the n channel MISFET (Qn and QN) forming areas of thefirst and second logic circuit areas are exposed is formed on thesemiconductor substrate 1. Then, a p type impurity such as boron or thelike is ion-implanted into the MISFET forming areas of the semiconductorsubstrate 1 with using the resist mask as a mask.

[0156] Next, after a removal of the resist film, a resist film (notshown) in which the p channel MISFET (Qp and QP) forming areas in thefirst and second logic circuit areas are exposed is formed on thesemiconductor substrate 1. Then, an n type impurity such as phosphorusor the like is ion-implanted into the MISFET forming areas of thesemiconductor substrate 1 with using the resist mask as a mask.

[0157] Next, after a removal of the resist film, a heat treatment isperformed relative to the semiconductor substrate 1, and thereby a deepn well 2 n, p wells 3 pm and 3 p, and an n well 3 n are formed in thesemiconductor substrate 1 as shown in FIG. 4.

[0158] In this embodiment, the deep n well 2 n is used to prevent noisefrom entering the p well 3 pm in the memory cell area from an I/Ocircuit or the like through the semiconductor substrate 1 and to preventthe electric charge accumulated in the memory cell from vanishing.However, it is also possible to use no deep n well 2 n in order toprevent the substrate voltage from being applied to the memory cellarea.

[0159] Next, a p type impurity such as BF₂ or the like for adjustment ofthe threshold voltage is ion-implanted into the n channel MISFET (Qn andQN) forming areas (p well 3 p) in the first and second logic circuitareas.

[0160] Next, an n impurity such as phosphorus or the like for adjustmentof the threshold voltage is ion-implanted into the p channel MISFET (Qpand QP) forming areas (n well 3 n) in the first and second logic circuitareas.

[0161] Next, a p type impurity such as boron or the like forpunch-through prevention is ion-implanted into the memory cell area.

[0162] In this embodiment, for simplification of processes, the ionimplantation for adjustment of the threshold voltage of the MISFETs (Qnand Qp) each having a later-described relatively thin gate insulatingfilm in the first logic circuit area, and the ion implantation foradjustment of the threshold voltage of the MISFETs (QN and QP) eachhaving a later-described relatively thick gate insulating film in thesecond logic circuit area are performed simultaneously and under thesame condition. However, these ion implantations for adjustment of thethreshold voltage can of course be performed under different conditionsand in different steps.

[0163] For example, after a p type impurity such as BF₂ or the like foradjustment of the threshold voltage is implanted into the n channelMISFET (Qn) forming area (p well 3 p) having a relatively thin gateinsulating film in the first logic circuit area, a p type impurity suchas BF₂ or the like for adjustment of the threshold voltage can be ofcourse ion-implanted into the n channel MISFET (QN) forming area (p well3 p) having a relatively thick gate insulating film in the second logiccircuit area.

[0164] In addition, after an n type impurity such as phosphorus or thelike for adjustment of the threshold voltage is ion-implanted into the pchannel MISFET (Qp) forming area (n well 3 n) having a relatively thingate insulating film in the first logic circuit area, an n type impuritysuch as phosphorus or the like for adjustment of the threshold voltagecan be of course ion-implanted into the p channel MISFET (QP) formingarea (n well 3 n) having a relatively thick gate insulating film in thesecond logic circuit area.

[0165] In this embodiment, the ion implantation for adjustment of eachthreshold voltage of the p channel MISFETs (Qp and QP) is used toappropriately set each threshold voltage. However, for thesimplification of the processes, it is of course possible to perform theion implantation simultaneously with the ion implantation for formingthe above-mentioned n well 3 n.

[0166] In this embodiment, for appropriate setting of the thresholdvoltage, the ion implantation for adjustment of each threshold voltageof the n channel MISFETs in the first and second logic circuit areas andthe ion implantation for the punch-through prevention of the memory cellselecting MISFET are performed in different steps. However, since thesubstrate concentration in the n channel MISFET and that of the memorycell selecting MISFET having a p type gate electrode are almost equal toeach other, it is of course possible to perform the ion implantationssimultaneously with each other under the same ion-implantationcondition.

[0167] Subsequently, a first thermal oxidation treatment is performedrelative to the semiconductor substrate 1, and thereby a gate insulatingfilm 8 k is formed on the semiconductor substrate 1 as shown in FIG. 5.A wet oxidation treatment at, for example, about 750° C. is employed inthis oxidation treatment. The gate insulating film 8 k at this stage hasa uniform thickness in all areas of the main surface of thesemiconductor substrate 1, and the thickness thereof is, for example,about 5.1 nm. Next, as shown in FIG. 6, a silicon oxide film 23 isdeposited on the semiconductor substrate 1 to a thickness of about 10 nmby the CVD method.

[0168] Next, a resist film 22 a in which the first logic circuit area(area for forming a relatively thin gate insulating film) is exposed isformed on the semiconductor substrate 1, and thereafter is used as anetching mask to remove the silicon oxide film 23 and the gate insulatingfilm 8 k. Thereby, both of the silicon oxide film 23 and the gateinsulating film 8 k are left only in the memory cell area and the secondlogic circuit area.

[0169] Subsequently, after the resist film 22 a is removed, the siliconoxide film 23 in the memory cell area and the second logic circuit areais removed by the known cleaning method. At this time, to prevent theremaining gate insulating film 8 k from being cut off, the silicon oxidefilm 23 is removed under the condition that the silicon oxide film 23has a high etching selective ratio with respect to the gate insulatingfilm.

[0170] Next, a second thermal oxidation treatment is performed relativeto the semiconductor substrate 1, and thereby gate insulating films 8 iand 8 j that are different from each other in thickness is formed on thesemiconductor substrate 1 as shown in FIG. 7. The wet oxidationtreatment at, for example, about 750° C. is employed in this oxidationtreatment.

[0171] Subsequently, an oxide nitridation treatment is performedrelative to the semiconductor substrate 1 by the known method. In thisstate, the gate insulating films 8 i and 8 j are different from eachother in thickness, and the thickness of the relatively thick gateinsulating film 8 j is, for example, about 6 nm and that of therelatively thin gate insulating film 8 i is, for example, about 3.5 nm.

[0172] Next, a polycrystalline silicon film 24 is deposited over thesemiconductor substrate 1 by the CVD method or the like as shown in FIG.8.

[0173] Subsequently, impurities are introduced into each gate electrodeof the MISFETs to be formed on the semiconductor substrate 1.

[0174] More specifically, as shown in FIG. 9, a resist film 22 b inwhich the n channel MISFET (Qn and QN) forming areas in the first andsecond logic circuit areas are exposed is formed on the polycrystallinesilicon film 24, and thereafter is used as a mask to ion-implant an ntype impurity such as phosphorus or arsenic (As) into thepolycrystalline silicon film 24 and to form n type polycrystallinesilicon areas 24 a.

[0175] Next, after a removal of the resist film 22 b, as shown in FIG.10, a resist film 22 c in which the p channel MISFET (Qp and QP) formingareas in the first and second logic circuit areas and the memory cellarea are exposed is formed on the polycrystalline silicon film 24 a, andis used as a mask to ion-implant a p type impurity such as boron or BF₂into the polycrystalline silicon film 24 and thereby form p typepolycrystalline silicon areas 24 b.

[0176] When the p type impurity such as boron or BF₂ or the like ision-implanted, it is preferable to control the implantation energy so asto prevent boron or the like from reaching a deep position in thepolycrystalline silicon film 24. This is because of the suppression of aphenomenon which is thought to easily occur, the phenomenon being onethat if the boron or the like reaches the deep position in thepolycrystalline silicon film 24, the boron penetrates the gateinsulating films 8 i and 8 j by the subsequent heat process and diffusesin the semiconductor substrate 1.

[0177] In this embodiment, to appropriately set the impurityconcentration of the gate electrodes (24 a and 24 b), when an n typeimpurity is ion-implanted into the polycrystalline silicon film 24 inthe n channel MISFET (Qn and QN) forming areas, other areas (the pchannel MISFET (Qp and QP) forming areas and the memory cell area) arecovered with the resist film 22. However, after an n type impurity ision-implanted into the whole area of the polycrystalline silicon film24, a resist film in which the p channel MISFET (Qp and QP) formingareas and the memory cell area are exposed may be formed thereon, and beused as a mask to ion-implant a p type impurity into the polycrystallinesilicon film 24.

[0178] In contrast, after a p type impurity is ion-implanted into thewhole area of the polycrystalline silicon film 24, a resist film inwhich the n channel MISFET (Qn and QN) forming areas and the memory cellarea are exposed may be formed thereon, and be used as a mask toion-implant an n type impurity into the polycrystalline silicon film 24.

[0179] As described above in this embodiment, since the conductive typeof the gate electrode is set at an n type or p type by the ionimplantation, it is possible to improve the characteristic of the gateelectrode. In addition, the conductive type of the gate electrode of thep channel MISFET constituting the logic circuit is set at a p type.Therefore, in the channel area of the p channel MISFET constituting thelogic circuit, an n type impurity having the same conductive type as thesubstrate in this channel area is ion-planted, and thereby it ispossible to adjust the threshold voltage of the p channel memory cellMISFET to a desired value.

[0180] Also, in a step of the ion implantation into the polycrystallinesilicon film 24, to prevent the boron penetration, nitrogen moleculeions may be implanted.

[0181] Subsequently, as shown in FIG. 11, a barrier metal film (notshown) made of, for example, tungsten nitride (WN) or the like isdeposited on the polycrystalline silicon films 24 a and 24 b, and then ametal film 25 made of, for example, tungsten or the like is depositedthereon.

[0182] Next, a silicon oxide film 6 is deposited on the metal film 25.Although the silicon oxide film 6 is used in this case, any film may beused if containing less amount of material, such as hydrogen or thelike, that promotes the boron penetration in comparison to the siliconnitride film.

[0183] Subsequently, a resist film (not shown) is formed on the siliconoxide film 6, and the silicon oxide film 6 is etched and thereby is leftas a hard mask in the area in which the gate electrode is to be formed.

[0184] Next, as shown in FIG. 12, the hard mask of the above-mentionedsilicon oxide film 6 is used as a mask to dry-etch the polycrystallinesilicon films 24 a and 24 b, the barrier metal film (not shown), and themetal film 25 and thereby form gate electrodes 5 g (word line WL), gateelectrodes 8 f, 8 g, 9 f, and 9 g. In this case, the gate insulatingfilms under the gate electrodes 8 f, 8 g, 5 g, 9 f and 9 g are referredas 8 i, 8 j, 5 i, 9 i and 9 j, respectively.

[0185] The gate electrode 5 g constitutes a part of the memory cellselecting MISFET and functions as the word line WL in the area otherthan the element forming area (on the isolation area).

[0186] A width of the gate electrode 5 g, namely, a gate length thereofis set to be the minimum dimension (e.g., 0.11 μm) within the allowablerange capable of suppressing the short channel effect of the memory cellselecting MISFET and keeping the threshold voltage higher than apredetermined value. Also, an interval between two adjacent gateelectrodes 5 g is set to be the minimum dimension (e.g., 0.11 μm)determined by the resolution limit of the photolithography.

[0187] The gate electrodes 8 f, 8 g, 9 f and 9 g constitute a part ofeach of the n channel MISFET and the p channel MISFET of the logiccircuit.

[0188] Next, the gate electrodes and the resist film are used as masksto implant impurities and thereby form semiconductor areas 5 a and 5 bin the memory cell area and semiconductor areas 8 c, 8 d, 9 cand 9 d inthe first and second logic circuit areas (FIG. 13).

[0189] More specifically, phosphorus is ion-implanted into the memorycell area (p well 3 pm) to about an implantation amount of 1 to2×10¹³/cm², and arsenic is ion-implanted into the p well 3 p of thefirst logic circuit area to an implantation amount of about 1 to2×10¹⁴/cm², and BF₂ or boron is ion-implanted into the n well 3 n of thefirst logic circuit area to an implantation amount of about 1 to2×10¹⁴/cm². In addition, to decrease the electric field from theviewpoint of measures for the hot-carrier effects, phosphorus ision-implanted into the p well 3 p of the second logic circuit area to animplantation amount of about 0.5 to 2×10¹⁴/cm², and BF₂ or boron ision-implanted into the n well 3 n of the second logic circuit area to animplantation amount of about 0.5 to 2×10¹⁴/cm². Then, the semiconductorsubstrate 1 is heated at 950° C. and for 10 seconds to activate theimplanted impurities and thereby form the semiconductor areas (5 a, 5 b,8 c, 8 d, 9 c and 9 d).

[0190] Next, as shown in FIG. 14, a silicon oxide film 7 is deposited toa thickness of 10 to 15 nm over the semiconductor substrate 1 by the CVDmethod. Although the silicon oxide film is used in this case, any filmmay be used if containing less amount of material, such as hydrogen orthe like, that promotes the boron penetration in comparison to a siliconnitride film.

[0191] Subsequently, a polycrystalline silicon film 24 is deposited onthe whole surface thereof by the CVD method, as shown in FIG. 15. Thefilm thickness of the polycrystalline silicon film 24 is set at such afilm thickness or more as to be capable of completely burying the spacesbetween the gate electrodes 5 g in the memory cell area. This embodimentis set at, for example, 80 nm.

[0192] Next, an anisotropic etching treatment is performed as shown inFIG. 16. By doing so, a insulating film 7 and a polycrystalline siliconfilms 24 c are left in the memory cell area, and a sidewall spacer film(hereinafter, referred to as sidewall film) 26 composed of the siliconoxide film 7 and the polycrystalline silicon film 24 c is formed on eachsidewall of the gate electrodes 8 f, 8 g, 9 f and 9 g in the first andsecond logic circuit areas. In order to minimize the cut-off amounts ofthe gate insulating films 8 i and 8 j or the like and the insulatingfilms 4 buried in the isolation area, this etching employs such etchinggas that an etching rate of the polycrystalline silicon film to thesilicon oxide film becomes high.

[0193] Thus, according to this embodiment, since the polycrystallinesilicon film is deposited and used as a hard mask in the memory cellarea, it is possible to reduce the photoresist step from the steps offorming the laminated sidewall film of the gate electrode in the logiccircuit area.

[0194] Subsequently, a resist film 22 d in which the n channel MISFET(Qn and QN) forming areas in the first and second logic circuit areasare exposed is formed over the semiconductor substrate 1. Thereafter, ann type impurity such as As is introduced by the ion implantation methodor the like with using, as masks, the resist film 22 d, the gateelectrodes 8 f and 8 g, and the laminated sidewall film 26 composed ofthe silicon oxide film 7 and the polycrystalline silicon film 24 c, andthereby a high-concentration semiconductor area 8 e is formed (FIG. 17).

[0195] Next, as shown in FIG. 18, an isotropic dry etching treatment isperformed relative to each polycrystalline silicon film 24 c of the nchannel MISFET forming areas in the first and second logic circuitareas, and thereby the polycrystalline silicon film 24 c is removed.This etching employs such etching gas that an etching rate of thepolycrystalline silicon film to the silicon oxide film becomes high.

[0196] In this embodiment, although the silicon oxide film 7 is left onthe semiconductor substrate 1 and on the sidewalls of the gateelectrodes 8 f and 8 g and the like, the silicon oxide film 7 along withthe polycrystalline silicon film 24 c can be of course removed.

[0197] Next, a resist film 22 e in which the p channel MISFET (Qp andQP) forming areas in the first and second logic circuit areas areexposed is formed over the semiconductor substrate 1. Thereafter, theresist film 22 e, the gate electrodes 9 f and 9 g, and the laminatedsidewall film 26 composed of both of the silicon oxide film 7 and thepolycrystalline silicon film 24 c are used as masks to introduce a ptype impurity such as boron by ion implantation and thereby form ahigh-concentration semiconductor area 9 e(FIG. 19).

[0198] Next, as shown in FIG. 20, an isotropic dry etching treatment isperformed relative to the polycrystalline silicon film 24 c of the pchannel MISFET forming areas in the first and second logic circuitareas, and thereby the polycrystalline silicon film 24 c is removed.This etching employs such etching gas that an etching rate of thepolycrystalline silicon film to the silicon oxide film becomes high.

[0199] In this embodiment, the silicon oxide film 7 is left on thesemiconductor substrate 1 and on the sidewall or the like of each of thegate electrodes 9 f and 9 g. However, it is of course possible to removethe silicon oxide film 7 along with the polycrystalline silicon film 24c.

[0200] Next, as shown in FIG. 21, a silicon oxide film 10 a is depositedto a thickness of about 0.7 μm over the semiconductor substrate 1, andthe surface unevenness located in an upper portion thereof and caused bythe gate electrodes is flattened by the known CMP method such that theheight thereof in all of the memory cell area and the first and secondlogic circuit areas is almost the same. Furthermore, polishing isperformed until the surface of the silicon oxide film 7 is exposed, andthereby the silicon oxide film 10 a on each of the gate electrodes(silicon oxide film 7) is removed completely as shown in FIG. 22.

[0201] Next, by the isotropic dry etching, the polycrystalline siliconfilm 24 c in the memory cell area is removed as shown in FIG. 23. Atthis time, in order to prevent the gate electrode from being exposed,the process of the polycrystalline silicon film is performed under thecondition that the polycrystalline silicon film have a high etchingselective ratio with respect to the silicon oxide film.

[0202] Subsequently, as shown in FIG. 24, the silicon oxide film 7 inthe memory cell area is removed by the anisotropic dry etching. As aresult, the silicon oxide film 7 on each of the cap insulating film 6and the surface of the semiconductor substrate 1 is removed, and thesilicon oxide film 7 is left only on each sidewall of the gate electrode5 g and the cap insulating film 6 in the memory cell area. The gateinsulating film 5 i on the semiconductor substrate 1 is also removed. Atthis time, in order to prevent the gate electrodes from being cut off,the process of the silicon oxide film is performed under the conditionthat the silicon oxide film has a high etching selective ratio withrespect to the silicon.

[0203] Next, an n type impurity such as phosphorus is furtherion-implanted into the semiconductor areas 5 a and 5 b exposed from thespaces between the gate electrodes 5 g in the memory cell area (notshown). This is an impurity introduction step for decreasing theelectric field.

[0204] Subsequently, a polycrystalline silicon film 12 containingimpurities with high concentration is coated on and over thesemiconductor substrate 1 as shown in FIG. 25.

[0205] Next, the surface unevenness located in the surface of thepolycrystalline silicon film 12 and caused by the gate electrodes isflattened by the known CMP method such that the height thereof in all ofthe memory cell area and the first and second logic circuit areas isalmost the same. Furthermore, polishing is performed until the capinsulating film 6 is exposed, and thereby the polycrystalline siliconfilm 12 on the gate electrodes (cap insulating film 6) is removedcompletely. As a result, the polycrystalline silicon film 12 is left oneach of the spaces between the gate electrodes 5 g in the memory cellarea.

[0206]FIG. 51 is a plan view showing the principal part of thesemiconductor substrate 1 after the polycrystalline silicon film 12 inthe memory cell area is formed. As shown in FIG. 51, the polycrystallinesilicon film 12 is separately formed in each of the spaces between thegate electrodes 5 g (word line).

[0207] Next, a photoresist FR (FIG. 52) is formed over the semiconductorsubstrate 1, the photoresist FR in which areas serving as the isolationarea in the memory cell area and having polycrystalline silicon betweenthe word lines (gate electrodes 5 g) are exposed. Thereafter, thephotoresist FR is used as a mask to remove the polycrystalline siliconfilm 12 located on each isolation area between the word lines. At thistime, in order to prevent the silicon oxide film on each of the gateelectrodes and the isolation area from being cut off, the process of thepolycrystalline silicon film is performed under the condition that thepolycrystalline silicon film has a high etching selective ratio withrespect to the silicon oxide film. As a result, polycrystalline siliconfilms 12 a and 12 b are formed separately on the semiconductor areas 5 aand 5 b between the gate electrodes 5 g (word line) (FIG. 26). Thepolycrystalline silicon films 12 a and 12 b function to connect the bitline BL or the capacitor C, and the source and drain (semiconductorareas 5 a and 5 b) of the memory cell selecting MISFET Q as describedabove. FIG. 27 is a plan view showing the principal part of thesemiconductor substrate 1 in the memory cell area after thepolycrystalline silicon films 12 a and 12 b are formed.

[0208] In this embodiment, from the viewpoint of easily forming theresist film, the photoresist is formed on and over the semiconductorsubstrate 1, the photoresist in which the areas serving as the isolationareas in the memory cell area and having the polycrystalline siliconfilm between the word lines are exposed, and thereafter the photoresistis used as a mask to remove the polycrystalline silicon film between theword lines. However, a photoresist in which the isolation area in thememory cell area is exposed can be of course formed on and over thesemiconductor substrate 1, and thereafter used as a mask to remove thepolycrystalline silicon film between the word lines.

[0209] Next, an interlayer insulating film 11 a made of, for example, asilicon nitride film is deposited on the whole surface of thesemiconductor substrate 1, and subsequently an interlayer insulatingfilm 10 b made of, for example, a silicon oxide film, is deposited onthe interlayer insulating film 11 a. The interlayer insulating film 11 afunctions as an etching stopper when the interlayer insulating film 10 bis etched.

[0210] Alumina (Al₂O₃) or silicon carbide (SiC) may be also used as anetching stopper for the silicon oxide film.

[0211] Next, a resist film (not shown) is formed on the interlayerinsulating film 10 b, and is used as an etching mask to etch theinterlayer insulating films 10 b and 11 a on the polycrystalline siliconfilm 12 b and thereby form a connection hole 13 c. The upper surface ofthe polycrystalline silicon film 12 b is exposed on the bottom surfaceof the connection hole 13 c.

[0212] Subsequently, after the resist film is removed, a resist film(not shown) is formed on the interlayer insulating film 10 b, and isused as an etching mask to etch the interlayer insulating films 10 a, 10b and 11 a and the like on the semiconductor areas 8a2, 8b2, 9a1 and 9b1and thereby form connection holes 15 c. The semiconductor areas 8a2,8b2, 9a1 and 9b1 are exposed on the bottom surfaces of the connectionholes 15 c, respectively.

[0213] Subsequently, after a removal of the resist film, for example, atitanium film and a titanium nitride film are sequentially depositedfrom below on the interlayer insulating film 10 b and in the connectionholes 13 c and 15 c by the sputtering method or the like, and thereby abarrier metal film 27 made of these films is formed. A tungsten film 25is, for example, stacked up thereon by the CVD method or the like, andthereby the connection holes 15 c are filled. Next, each upper portionof these films is polished by the known CMP method until the upperportion of the interlayer insulating film 10 b is exposed and respectivetungsten films 26 and the like in the connection holes 13 c and 15 chave the same height. As a result, a contact electrode 13 composed ofthe barrier metal film 27 and the tungsten film 25 is formed on thepolycrystalline silicon film 12 b, and also contact electrodes 15composed of the barrier metal film 27 and the tungsten film 25 areformed on the semiconductor areas 8a2, 8b2, 9a1 and 9b1.

[0214] Next, an interlayer insulating film 11 b made of, for example,silicon nitride is formed on the whole surface of the semiconductorsubstrate 1, and further an interlayer insulating film 10 c made of, forexample, silicon oxide is deposited thereon. The above-mentionedinterlayer insulating film 11 b functions as an etching back stopperwhen the interlayer insulating film 10 c is etched.

[0215] Then, a resist film (not shown) having openings on the contactelectrodes 13 and 15 is formed on the interlayer insulating film 10 c,and is used as an etching mask to etch the interlayer insulating films10 c and 11 b and thereby form a bit line trench and a first-layerwiring trench.

[0216] Next, an insulating film such as a silicon oxide film isdeposited to a thickness of about 200 nm on the interlayer insulatingfilm 10 c and in the bit line trench and the first-layer wiring trench.By the anisotropic etching, sidewalls (not shown) are formed on theinner side surfaces of the bit line trench and the first-layer wiringtrench. Thus, since the sidewall is formed in the bit line trench, it ispossible to make the bit line BL thin and prevent the later-describedshort circuit between the contact electrode 12 c and the bit line BL.

[0217] Next, a titanium film and a titanium nitride film aresequentially deposited from below on the interlayer insulating film 10 cand in the bit line trench and the first-layer wiring trench by thesputtering method or the like, and thereby a barrier metal film 27composed of these films is formed. Further, a tungsten film 25 is, forexample, stacked up thereon by the CVD method or the like. Subsequently,these films are etched-back until the upper surface of the interlayerinsulating film 10 c is exposed and the upper surfaces of the tungstenand the like have each the same height, and thereby the bit line BL andthe first-layer wirings 14 a and 14 b are formed (FIG. 28).

[0218] Subsequently, a silicon nitride oxide film or an aluminum 11 c isdeposited to a thickness of about 0.7 μm over the semiconductorsubstrate 1. Subsequently, a polycrystalline silicon film (not shown) isdeposited thereon. Then, the polycrystalline silicon film located on thepolycrystalline silicon film 12 a is removed by the etching, and therebya polycrystalline silicon hard mask (not shown) is formed.

[0219] Subsequently, a polycrystalline silicon film is further depositedon the polycrystalline silicon hard mask, and a polycrystalline sidewall(not shown) is formed on the sidewall of the polycrystalline siliconhard mask by the back etching. Thus, the use of the sidewall (not shown)makes it possible to make the connection holes fine, and prevent shortcircuit between the bit line BL and the later-described contactelectrode 12 c.

[0220] Next, the polycrystalline silicon hard mask and the sidewall (notshown) is used to remove the interlayer insulating films 11 a, 10 b, 11b, 10 c and 11 c on each contact electrode 12 a, and thereby form aconnection hole.

[0221] Subsequently, a polycrystalline silicon film 12 c containingimpurities with a high concentration is deposited over the semiconductorsubstrate 1, and the etch back of the polycrystalline silicon film 12 cis performed under the condition that the polycrystalline silicon film12 c has a high etching selective ratio with respect to the interlayerinsulating film 11 c, and thereby the upper portion of the interlayerinsulating film 11 c is exposed. After the complete isolation of thepolycrystalline silicon film 12 c buried in the above-mentionedconnection hole, the etch back of the surface of the polycrystallinesilicon film 12 c is performed to a depth of about 0.1 μm.

[0222] Next, an oxidation barrier film 16 made of, for example, tantalumnitride is deposited over the semiconductor substrate 1, and the etchback of the oxidation barrier film 16 is performed by the known CMPmethod until the upper portion of the interlayer insulating film 11 c isexposed, and thereby an oxidation barrier film 16 is formed on thepolycrystalline silicon film 12 c (FIG. 29). Note that FIG. 29 shows thebit line BL extending between two polycrystalline silicon films 12 c.Also, although a tantalum nitride film is used as the oxidation barrierfilm 16 in this embodiment, a titanium nitride film may be used.

[0223] In this embodiment, since ruthenium is used as an electrode ofthe capacitor C as described later, the oxidation barrier film 16 isformed thereon to prevent the oxidation of polycrystalline silicon film12 c. However, only polycrystalline silicon can be, of course, used toform a contact in the case of using polycrystalline silicon or the likeas an electrode of the capacitor C.

[0224] Next, to form a three-dimensional capacitor electrode, a siliconoxide film 10 d used as an interlayer insulating film is deposited to athickness of about 1.4 μm, and a tungsten hard mask (not shown) isformed thereon. Thereafter, the silicon oxide film 10 d is dry-etched,and thereby a deep trench is formed in the oxidation barrier film 16.

[0225] Next, a ruthenium film to be a storage electrode 17 a of thecapacitor C is deposited to, for example, a thickness of about 30 nm onthe silicon oxide film 10 d and in the deep trench. The use of the metalsuch as ruthenium or the like as a material of the lower electrode ofthe capacitor makes it possible to decrease the annealing temperaturefor forming the capacitor to 600° C. or lower. As a result, thepenetration of boron that is an impurity in the gate electrode can bereduced.

[0226] As a material of the storage electrode 17 a of the capacitor,polycrystalline silicon, tungsten, titanium nitride, platinum or thelike are also used in addition to ruthenium. Particularly, platinum ispreferable as a material of the storage electrode when a highpermittivity film such as BST (strontium barium titanate) and PZT (leadzirconate titanate) or a ferro-electric film is used film.

[0227] Subsequently, the etch back of the ruthenium film on the siliconoxide film 10 d is performed by the CMP method, and thereby the storageelectrodes 17 a is left only in the deep trenches to form the storageelectrode 17 a separately in each memory cell.

[0228] Next, a capacitor insulating film 17 b made of, for example,tantalum oxide is formed on the surface of the storage electrode 17 a,and further a plate electrode 17 c made of, for example, ruthenium isformed thereon so as to cover the capacitor insulating film 17 b.

[0229] Note that the material of the capacitor insulating film is notlimited to tantalum oxide. The conventional laminated film of a siliconoxide film and a silicon nitride film may be used, or a highpermittivity film or a ferroelectric film may be used when platinum as amaterial of the storage electrode is used.

[0230] Subsequently, a titanium nitride film 17 d and a tungsten film 17e are deposited on the plate electrode 17 c, and the pattering thereofis performed with using a tungsten hard mask (not shown) to form plateelectrode wirings (17 c, 17 d and 17 e) (FIG. 30).

[0231] Next, an interlayer insulating film 10 e is deposited so as tocover the plate electrode wirings (17 c, 17 d and 17 e). Subsequently,the dry etching is performed with using a tungsten hard mask (notshown), and thereby connection holes 19 c are formed on the tungstenfilm 17 e in the memory cell area and on the first-layer wirings 14 aand 14 b in the first and second logic circuit areas.

[0232] Subsequently, a titanium film and a titanium nitride film aredeposited from below by the sputtering method or the like, and a barriermetal film 27 composed of these films is formed. Then, a tungsten film25 is stacked up thereon by the CVD method or the like to fill theconnection hole 19 c. Next, the etch back of each of these films isperformed by the known CMP method to form contact electrodes 19.

[0233] Next, a barrier metal film 27, an aluminum film 28, and a barriermetal film 27 are sequentially deposited and then patterned, therebyforming second-layer wirings 18 a and 18 b on the contact electrodes 19(FIG. 31). Of course, it is also possible to use metal having a lowerresistance, such as copper or the like, instead of aluminum.

[0234] Subsequently, a silicon oxide film 10 f is deposited by ahigh-density CVD method, and then a CVD silicon oxide film 10 g having agood embedded characteristic is deposited. Thereafter, the upper portionthereof is flattened by the known CMP method.

[0235] Next, an interlayer insulating film 10 h is deposited, and thenthe interlayer insulating films 10 f, 10 g and 10 h are etched to formconnection holes 21.

[0236] Next, for example, a titanium film and a titanium nitride filmare sequentially deposited from below by the sputtering method or thelike, and a barrier metal film 27 composed of these films is formed.Then, for example, a tungsten film 25 is stacked up thereon by the CVDmethod or the like to fill the connection holes 21 c. Subsequently, theetching back is performed by the known CMP method, and thereby contactelectrodes 21 are formed.

[0237] Subsequently, a barrier metal film 27, an aluminum film 28, and abarrier metal film 27 are sequentially deposited and etched, and therebyuppermost-layer wirings 20 are formed (FIG. 32).

[0238] Note that a passivation film composed of two insulating films andthe like made by, for example, laminating a silicon oxide film and asilicon nitride film is formed on third-layer (uppermost layer) wirings20. However, the illustrations thereof will be omitted.

[0239] According to this embodiment described above, since a siliconoxide film is used for both of the cap insulating film 6 on the gateelectrodes and the sidewall film 7 on each sidewall of the gateelectrodes, it is possible to reduce the stored amount of hydrogen andammonia and the like promoting the boron penetration in comparison tothe case of using a silicon nitride film and also reduce an emissionamount of these. Therefore, the penetration of boron, which is animpurity in the gate electrodes, into the substrate is suppressed, andthus the variance of the threshold voltage and the degradation of thegate blocking voltage can be reduced. In addition, with using the capinsulating film 6 and the sidewall film 7, since the etch back of the ntype polycrystalline silicon film deposited on the surface of thesubstrate is performed by the CMP method and the n type polycrystallinesilicon film is separated, the contact electrodes 12 a and 12 bconnected to the bit line BL and the capacitor C can be formed in aself-alignment manner. Also, it is unnecessary to form a connection holeused to form a contact electrode.

[0240] Further, since a p type polycrystalline silicon gate electrodehaving a high work function is used for the memory cell selecting nchannel MISFET Q, it is unnecessary to introduce the impurities foradjustment of the threshold voltage and thus reduce the substrateconcentration. Therefore, since the electric field near the junction ofthe connection of the semiconductor areas to be connected to thecapacitor is decreased and the leakage currents of the storage node andthe semiconductor substrate is reduced, it is possible to improve therefresh characteristic thereof.

[0241] In addition, since the ion implantation of boron is employed, thep type polycrystalline silicon gate electrode having a desirableimpurity concentration can be formed.

[0242] Further, when the p type polycrystalline silicon gate electrodeis used in each p channel MISFET of the first and second logic circuitareas, the channel thereof is a surface type. Therefore, the downsizingof the p channel MISFET is facilitated and the performance of the pchannel MISFET can be improved.

[0243] Also, since a laminated film of the silicon oxide film 7 and thepolycrystalline silicon film 24 c is used for the sidewall film 26 onthe sidewall of the gate electrode in the logic circuit area, it ispossible to form the sidewall film 26 thicker in thickness than thesidewall film on the sidewall of the gate electrode in the memory cellarea and thus form the source and drain of the LDD structure with highaccuracy. As a result, it is possible to achieve the downsizing of theMISFET constituting the logic circuit and the improvement of thereliability thereof.

[0244] (Second Embodiment)

[0245] This embodiment relates to a production process for the sourceand drain (semiconductor area) in the logic circuit area. In the firstembodiment, to simplify the process, the high concentrationsemiconductor area is formed after the (low concentration) semiconductorarea is formed in the first and second logic circuit areas.

[0246] In contrast, in this second embodiment, the low concentrationsemiconductor area is formed after the high concentration semiconductorarea is formed in the logic circuit area.

[0247] Since the production method until the process of dry-etching thegate electrode in this embodiment is the same as that in the firstembodiment described with reference to FIGS. 2 to 12, the descriptionsthereof will be omitted.

[0248] First, the semiconductor substrate 1 shown in FIG. 12 describedin the first embodiment is prepared, and impurities are implanted withusing the gate electrode and a resist film (not shown) as masks, andthereby the semiconductor areas 5 a and 5 b are formed in the memorycell area (FIG. 33). More specifically, phosphorus is ion-implanted intothe memory cell area (p well 3 pm) to an implantation amount of 1 to2×10¹³/cm².

[0249] Next, as shown in FIG. 34, a silicon oxide film 7 is deposited toa thickness of 10 to 15 nm on and over the semiconductor substrate 1 bythe CVD method. In this case, although a silicon oxide film is used, anyfilm may be used if containing less amount of material such as hydrogenor the like that promotes the boron penetration in comparison to thesilicon nitride film.

[0250] Next, as shown in FIG. 35, a polycrystalline silicon film 24 isdeposited to a thickness of about 80 nm on the silicon oxide film 7 bythe CVD method. The thickness of the polycrystalline silicon film 24 isset at a thickness equal to or thicker than the thickness capable ofcompletely burying the spaces between the gate electrodes 5 g in thememory cell area, and, in this embodiment, is set at, for example, 80nm.

[0251] Next, an anisotropic dry etching treatment is performed as shownin FIG. 36. Thereby, the insulating film 7 and the polycrystallinesilicon film 24 c are left in the memory cell area, and the sidewallfilm 26 composed of the silicon oxide film 7 and the polycrystallinesilicon film 24 c is formed on each sidewall of the gate electrodes 8 f,8 g, 9 f and 9 g in the first and second logic circuit areas.

[0252] In order to minimize the cut-off amount of the gate insulatingfilms 8 i and 8 j and the like and that of the insulating film 4 buriedin the isolation area, this etching employs such etching gas that aetching rate of the polycrystalline silicon film to the silicon oxidefilm becomes high.

[0253] Subsequently, a resist film 22 d in which the n channel MISFET(Qn and QN) forming areas in the first and second logic circuit areasare exposed is formed over the semiconductor substrate 1. Thereafter,the resist film 22 d, the gate electrodes 8 f and 8 g, and the laminatedsidewall film 26 composed of both of the silicon oxide film 7 and thepolycrystalline silicon film 24 c are used as masks to introduce an ntype impurity such as As by the ion implantation method or the like andthereby form high-concentration semiconductor areas 8 e (FIG. 37).

[0254] Next, as shown in FIG. 38, an isotropic dry etching treatment isperformed relative to the polycrystalline silicon film 24 c of the nchannel MISFET forming areas in the first and second logic circuitareas, and thereby the polycrystalline silicon film 24 c is removed.Subsequently, an isotropic dry etching treatment is performed relativeto the silicon oxide film 7, and thereby the silicon oxide film 7 isremoved.

[0255] Next, a resist film 22 e in which the p channel MISFET formingareas in the first and second logic circuit areas are exposed is formedon and over the semiconductor substrate 1. Thereafter, the resist film22 e, the gate electrodes 9 f and 9 g, and the laminated sidewall film26 composed of both of the silicon oxide film 7 and the polycrystallinesilicon film 24 c are used as masks to introduce a p type impurity suchas boron or BF₂ by the ion implantation and thereby formhigh-concentration semiconductor areas 9 e (FIG. 39).

[0256] Next, as shown in FIG. 40, an isotropic dry etching treatment isperformed relative to the polycrystalline silicon film 24 c of the pchannel MISFET forming area in the first and second logic circuit areas,and thereby the polycrystalline silicon film 24 c is removed.Subsequently, an isotropic dry etching treatment is performed relativeto the silicon oxide film 7, and thereby the silicon oxide film 7 isremoved.

[0257] Next, the gate electrodes and the resist film (not shown) areused as masks to implant impurities and thereby form thelow-concentration semiconductor areas 8 c, 8 d, 9 c and 9 d in the firstand second logic circuit areas (FIG. 41).

[0258] More specifically, arsenic is ion-implanted into the p well 3 pof the first logic circuit area to an implantation amount of 1 to2×10¹⁴/cm², and BF₂ or boron is ion-implanted into the n well 3 n of thefirst logic circuit area to an implantation amount of 1 to 2×10¹⁴/cm².In addition, from the viewpoint of the measures for the hot-carriereffects, phosphorus capable of decreasing the electric field ision-implanted into the p well 3 p of the second logic circuit area to animplantation amount of 0.5 to 2×10¹⁴/cm², and BF₂ or boron ision-implanted into the n well 3 n of the second logic circuit area to animplantation amount of 0.5 to 2×10¹⁴/cm². Then, the semiconductorsubstrate is heated at 950° C. for 10 seconds to activate the implantedions and thereby form the semiconductor areas 8 c, 8 d, 9 c and 9 d.

[0259] Next, as shown in FIG. 42, a silicon oxide film 10 a is depositedto a thickness of about 0.7 μm on and over the semiconductor substrate1. The later-following production process is the same as that describedwith reference to FIGS. 22 to 32 in the first embodiment. Therefore, thedescription thereof will be omitted.

[0260] In this embodiment, the low-concentration semiconductor area inthe first and second logic circuit areas is formed after thehigh-concentration semiconductor area in these semiconductor areas isformed. Therefore, it is possible to form the low-concentrationsemiconductor area with high performance. More specifically, in the caseof forming the high-concentration semiconductor area after thelow-concentration semiconductor area in the logic circuit area isformed, ions in the low-concentration semiconductor area are affected atthe time of the ion implantation for forming the high-concentrationsemiconductor area, and consequently the characteristic thereof isdeteriorated. In this embodiment, however, the low-concentrationsemiconductor area is formed after the high-concentration semiconductorarea is formed. Therefore, the characteristic of the MISFET can beimproved.

[0261] (Third Embodiment)

[0262] A third embodiment relates to the formation of the contactelectrodes in the memory cell area. In the first embodiment, thehigh-concentration semiconductor area in the logic circuit area isformed after the polycrystalline silicon film 24 is formed, and furtherthe polycrystalline silicon film 24 c is removed. The removal of thepolycrystalline silicon film 24 c is performed to further ion-implant ann type impurity such as phosphorus into the semiconductor areas 5 a and5 b and form the contact electrodes (12 a and 12 b) on the semiconductorareas 5 a and 5 b.

[0263] In contrast, in this embodiment, the n type polycrystallinesilicon film is deposited on the semiconductor substrate after thesource and drain (semiconductor areas) of the memory cell selectingMISFET Q are exposed.

[0264] Since the production process until the step of forming thesilicon oxide film 7 in this embodiment is the same as that in the firstembodiment described with reference to FIGS. 2 to 14, the descriptionsthereof will be omitted.

[0265] First, the semiconductor substrate 1 described in the firstembodiment and shown in FIG. 14 is prepared. Next, as shown in FIG. 43,a resist film 22 f in which the memory cell forming area is exposed isformed thereon, and is used as a mask to perform an anisotropic etchingtreatment relative to the silicon oxide film 7. As a result, the siliconoxide film 7 on the upper surface of the cap insulating film 6 and thaton the semiconductor substrate 1 are removed, and the silicon oxide film7 is left only on the respective sidewalls of the gate electrodes 5 gand the cap insulating film 6 in the memory cell area. At this time, inorder to prevent the gate electrodes from being cut off, the removal ofthe silicon oxide film 7 is performed under the condition that thesilicon oxide film 7 has a high etching selective ratio with respect tothe silicon.

[0266] Next, the anisotropic dry etching treatment is performed relativeto the gate insulating film 5 i to remove the gate insulating film 5 iand thereby expose the semiconductor areas 5 a and 5 b.

[0267] Next, an n type impurity such as phosphorus is ion-implanted intothe semiconductor areas 5 a and 5 b exposed from the spaces between thegate electrodes 5 g in the memory cell area (not shown). This impurityintroduction process is performed with an aim to decrease the electricfield.

[0268] Next, the polycrystalline silicon film 24 c is deposited on thewhole surface thereof by the CVD method as shown in FIG. 44. Thethickness of the polycrystalline silicon film 24 c is equal to or morethan the thickness capable of completely burying the spaces between thegate electrodes 5 g in the memory cell area, and, in this embodiment, isset at, for example, 80 nm.

[0269] Next, the anisotropic dry etching treatment is performed as shownin FIG. 45. Thereby, the insulating film 7 and the polycrystallinesilicon film 24 c are left in the memory cell area, and the sidewallfilm 26 composed of the silicon oxide film 7 and the polycrystallinesilicon film 24 c is formed on each sidewall of the gate electrodes 8 f,8 g, 9 f and 9 g in the first and second logic circuit areas. Of thepolycrystalline silicon film 24 c left in the memory cell area, thepolycrystalline silicon film 24 c on each semiconductor area 5 afunctions as a connection electrode for the bit line BL, and thepolycrystalline silicon film 24 c on the semiconductor area 5 bfunctions as a connection electrode for the capacitor C.

[0270] In order to minimize the cut-off amount of the gate insulatingfilms 8 i and 8 j and the like and the cut-off amount of the insulatingfilm 4 buried in the isolation area, this etching employs such etchinggas that an etching rate of the polycrystalline silicon film of thesilicon oxide film becomes high.

[0271] Next, similarly to the first embodiment, the high-concentrationsemiconductor areas 8 e are formed in the n channel MISFET (Qn and QN)forming areas of the first and second logic circuit areas, and thepolycrystalline silicon film 24 c formed in these areas is removed.Subsequently, the high-concentration semiconductor areas 9 e are formedin the p channel MISFET forming areas of the first and second logiccircuit areas, and the polycrystalline silicon film 24 c in these areasis removed.

[0272] Thus, according to this embodiment, the polycrystalline siliconfilm with high impurity concentration is deposited on the surfacethereof while the semiconductor areas of the memory cell selectingMISFET are exposed, and thereby the contact electrode (polycrystallinesilicon film 24 c) is formed. Therefore, in the logic circuit area, thesemiconductor area can be formed with using the polycrystalline siliconfilm 24 c as a sidewall film. As described above, the sidewall films,each of which is different in thickness, can be formed in the memorycell area and the logic circuit area, respectively. Therefore, it ispossible to form the MISFET having a good characteristic.

[0273] Next, as shown in FIG. 46, the silicon oxide film 10 a isdeposited to a thickness of about 0.7 μm on and over the semiconductorsubstrate 1, and is polished until the surface of the cap insulatingfilm 6 is exposed.

[0274] The later-following production process is the same as that theproduction process in the first embodiment with reference to FIGS. 26 to32. Therefore, the descriptions thereof will be omitted.

[0275] Thus, in this embodiment, the source and drain (semiconductorareas) in the memory cell area are exposed, and thereafter the n typepolycrystalline silicon film 24 is deposited, and the source and drain(semiconductor areas) in the logic circuit area are formed. Therefore,it is possible to use the polycrystalline silicon film 12 left in thememory cell area, as each of connection electrodes for the bit line BLand the capacitor C. As a result, it is possible to eliminateundesirable damages to the removal and the further burying of thepolycrystalline silicon film 24 c.

[0276] (Fourth Embodiment)

[0277] A fourth embodiment relates to the sidewall film formed on thesidewall of the gate electrode. In the first embodiment and the like,the sidewall film 26 is composed of the silicon oxide film 7 and thepolycrystalline silicon film 24 c. In the fourth embodiment, thesidewall film is formed by depositing two kinds of insulating films.

[0278] Since the production process until the step of forming thelow-concentration semiconductor area in this embodiment is the same asthat in the first embodiment described with reference to FIGS. 2 to 13,the descriptions thereof will be omitted.

[0279] First, the semiconductor substrate 1 described in the firstembodiment and shown in FIG. 13 is prepared. Next, as shown in FIG. 47,the silicon oxide film 7 a is deposited to a thickness of about 80 nm onthe whole surface of the substrate by the CVD method.

[0280] Next, as shown in FIG. 48, a resist film 22 f in which the memorycell area is exposed is formed, and is used as a mask to perform adry-etching treatment relative to the silicon oxide film 7 a and therebyremove the silicon oxide film 7 a in the memory cell area.

[0281] Subsequently, the resist film 22 f is removed. As shown in FIG.49, the silicon oxide film 7 b is deposited on the whole surface of thesubstrate by the CVD method. Next, an anisotropic dry etching treatmentis performed. As a result, the sidewall films, each of which isdifferent in thickness, are formed on the sidewalls of the gateelectrodes 5 g in the memory cell area and on the sidewalls of the gateelectrodes 8 f, 8 g, 9 f and 9 g in the first and second logic circuitareas, respectively. More specifically, the sidewall film composed ofthe silicon oxide film 7 b is left on each of the sidewalls of the gateelectrodes in the memory cell area, and the sidewall films composed ofthe silicon oxide films 7 a and 7 b are left on the sidewalls of thegate electrodes in the first and second logic circuit areas,respectively.

[0282] In this case, the thickness of the first layer (7 a) of thelaminated sidewall film in the logic circuit area is selected so thatthe MISFET constituting the logic circuit can have a goodcharacteristic. In this embodiment, the thickness thereof is set, forexample, at 80 nm.

[0283] Also, the thickness of the second layer (7 b) of the laminatedsidewall film in the logic circuit area is selected so that the memorycell selecting MISFET can have a good characteristic. In thisembodiment, the thickness thereof is set, for example, within a range of10 to 15 nm.

[0284] In addition, it is of course possible to use different materialsfor the first and second layers of the laminated sidewall film in thelogic circuit area. For example, as shown in FIG. 50, the siliconnitride film 47 a may be used as the first layer and the silicon oxidefilm 7 b may be used as the second layer. Also, a silicon nitride filmmay be used as the cap insulating film 6.

[0285] The later-following production process in this embodiment is thesame as that described in the first embodiment with reference to FIGS.17 to 32. Therefore, the descriptions thereof will be omitted. However,the step of removing the polycrystalline silicon film 24 c in the firstembodiment is unnecessary.

[0286] Thus, according to the embodiment, the sidewall film formed bylaminating two kinds of insulating films is used as the sidewall film oneach sidewall of the gate electrodes in the logic circuit areas, and socan be formed more thickly than the sidewall film on each sidewall ofthe gate electrodes in the memory cell area. Thus, it is possible toform the source and drain of the LDD structure with high accuracy. As aresult, it is possible to achieve the downsizing of the MISFETconstituting each logic circuit and the improvement of the reliabilitythereof. Further, if the two kinds of insulating films are used as thesilicon oxide film, the boron penetration can be prevented.

[0287] Also, if the silicon nitride film is used as the first layer andthe silicon oxide film is used as the second layer, it is possible toform the contact electrode in the logic circuit area in a self-alignmentmanner.

[0288] Also, it is possible to form the contact electrodes connected tothe bit line BL and the capacitor C in a self-alignment manner, by usingthe cap insulating film and the sidewall film.

[0289] In the foregoing, the inventions made by the inventors thereofhave been described based on the embodiments. However, it goes withoutsaying that the present invention is not limited to the foregoingembodiments and can be variously changed and modified without departingfrom the gist or scope thereof.

[0290] The advantages achieved by the typical ones of the inventionsdisclosed in this application will be briefly described as follows.

[0291] (1) According to the present invention, since the p type gateelectrode is used in the memory cell selecting n channel MISFET, it ispossible to increase the threshold voltage of the n channel memory cellselecting MISFET without increasing the impurity concentration of thesemiconductor substrate.

[0292] (2) According to item (1) mentioned above, it is possible to omitthe step of ion-implanting the impurities into the channel area of the nchannel memory cell selecting MISFET constituting the memory cell.

[0293] (3) According to the present invention, since a film such as thesilicon oxide film containing no hydrogen or little hydrogen is used asthe insulating film on the gate electrode and as the first film of thesidewall on the gate electrode, the boron penetration from the gateelectrode is prevented. Particularly, it is possible to improve thecharacteristic of the p channel MISFET formed in the peripheral circuitforming area.

[0294] (4) According to the present invention, the first and secondfilms are left on the sidewalls of the gate electrodes of the n channelMISFET and the p channel MISFET formed in the peripheral circuit formingareas, and the first and second films are used as masks to implant theimpurities into both sides of each gate electrode of the n channelMISFET and the p channel MISFET described above and thereby form thesemiconductor areas. Therefore, the sidewall film on the sidewall of thegate electrode in the peripheral circuit forming area can be formed morethickly than the sidewall film on the sidewall of the gate electrode inthe memory cell area, and each characteristic of the n channel MISFETand the p channel MISFET that constitute the logic circuit can beimproved.

[0295] (5) According to the present invention, metal is used in thelower electrode and the upper electrode of the capacitor constitutingthe memory cell (so-called MIM structure). Therefore, the annealingtemperature at the time of forming the capacitor can be set at 600° C.or lower, and the boron penetration can be prevented.

[0296] (6) According to the present invention, since the open bit linearrangement is employed in the memory cell, it is possible to make thememory cell highly integrated.

What is claimed is:
 1. A production method of a semiconductor integratedcircuit device having: a memory cell composed of a memory cell selectingn channel MISFET and a capacitor which are formed in a memory cellforming area of a semiconductor substrate; and an n channel MISFET and ap channel MISFET which are formed in a peripheral circuit forming area,said production method comprising: (a) a step of forming a gateinsulating film on said semiconductor substrate; (b) a gate electrodeforming step of forming a silicon film and an insulating film on saidgate insulating film, and forming, by patterning, gate electrodes of amemory cell selecting n channel MISFET, an n channel MISFET, and a pchannel MISFET and insulating films on the upper portions thereof,wherein said gate electrode forming step comprises the steps of:introducing a p type impurity into a silicon film constituting the gateelectrode of said memory cell selecting n channel MISFET and the gateelectrode of said p channel MISFET; and introducing an n type impurityinto a silicon film constituting the gate electrode of said n channelMISFET; (c) a step of sequentially depositing a first film and a secondfilm on said semiconductor substrate, and leaving, by performing ananisotropic etching, the first and second films on a sidewall of thegate electrode in said peripheral circuit forming area, and fillingspaces between said gate electrodes in said memory cell forming area,with said first and second films; and (d) a step of using said first andsecond films as a mask to implant an impurity into both sides of each ofthe gate electrodes of said n channel MISFET and said p channel MISFETand thereby form a semiconductor area.
 2. The production methodaccording to claim 1, further comprising: a step of removing said secondfilm in the memory cell forming area and thereafter removing said firstfilm on said semiconductor substrate; and a step of filling, with aconductive film, a space between the gate electrodes of said memory cellselecting n channel MISFET and thereby form a contact electrode.
 3. Theproduction method according to claim 2, wherein said contact electrodeis formed by the steps of depositing said conductive film on the gateelectrodes and between the gate electrodes, and polishing saidconductive film on said gate electrodes until the first film on saidgate electrode is exposed.
 4. A production method of a semiconductorintegrated circuit device having: a memory cell composed of a memorycell selecting n channel MISFET and a capacitor which are formed in amemory cell forming area of a semiconductor substrate; and an n channelMISFET and a p channel MISFET which are formed in a peripheral circuitforming area, said production method comprising: (a) a step of forming agate insulating film on said semiconductor substrate; (b) a gateelectrode forming step of forming a silicon film and an insulating filmon said gate insulating film, and forming, by patterning, gateelectrodes of a memory cell selecting n channel MISFET, an n channelMISFET, and a p channel MISFET and insulating films on the upperportions thereof, wherein said gate electrode forming step comprises thesteps of: introducing a p type impurity into a silicon film constitutingthe gate electrode of said memory cell selecting n channel MISFET andthe gate electrode of said p channel MISFET; and introducing an n typeimpurity into a silicon film constituting the gate electrode of said nchannel MISFET; (c) a step of using, as a mask, the gate electrode ofsaid memory cell selecting n channel MISFET and the insulating film onthe upper portion thereof to implant an impurity into the both sides ofsaid gate electrode and thereby form a first semiconductor area in thesemiconductor substrate of the memory cell forming area; (d) a step ofsequentially depositing a first film and a second film on saidsemiconductor substrate, and leaving, by performing an anisotropicetching, the first and second films on a sidewall of the gate electrodein said peripheral circuit forming area, and filling spaces between saidgate electrodes in said memory cell forming area, with said first andsecond films; (e) a step of using, as a mask, said first and secondfilms to implant an impurity into both sides of each of the gateelectrodes of said n channel MISFET and said p channel MISFET andthereby form a second semiconductor area; and (f) a step of using, as amask, the gate electrodes of said n channel MISFET and p channel MISFETand the insulating films on the upper portions thereof to implant animpurity into both sides of each of said gate electrodes and therebyform a third semiconductor area having a impurity concentration lowerthan said second semiconductor area in the semiconductor substrate ofthe memory cell forming area.
 5. A production method of a semiconductorintegrated circuit device having: a memory cell composed of a memorycell selecting n channel MISFET and a capacitor which are formed in amemory cell forming area of a semiconductor substrate; and an n channelMISFET and a p channel MISFET which are formed in a peripheral circuitforming area, said production method comprising: (a) a step of forming agate insulating film on said semiconductor substrate; (b) a gateelectrode forming step of forming a silicon film and an insulating filmon said gate insulating film, and forming, by patterning, gateelectrodes of a memory cell selecting n channel MISFET, an n channelMISFET, and a p channel MISFET and insulating films on the upperportions thereof, wherein said gate electrode forming step comprises thesteps of: introducing a p type impurity into a silicon film constitutingthe gate electrode of said memory cell selecting n channel MISFET andthe gate electrode of said p channel MISFET; and introducing an n typeimpurity into a silicon film constituting the gate electrode of said nchannel MISFET; (c) a step of depositing a first film on saidsemiconductor substrate, and removing said first film on saidsemiconductor substrate in the memory cell forming area; (d) a step ofdepositing a second film on said first film and said semiconductorsubstrate, and leaving, by performing an anisotropic etching, the firstand second films on a sidewall of said gate electrode in said peripheralcircuit forming area, and filling spaces between said gate electrodes insaid memory cell forming area and on said semiconductor substrate, withsaid second film; and (e) a step of using, as a mask, said first andsecond films to implant an impurity into both sides of each of the gateelectrodes of said n channel MISFET and said p channel MISFET andthereby form a semiconductor area.
 6. The production method according toclaim 1, wherein each of said insulating film and said first film is afilm containing one of no hydrogen and little hydrogen.
 7. Theproduction method according to claim 1, wherein said first film is asilicon oxide film and said second film is a silicon film.
 8. Theproduction method according to claim 1, wherein said first film is afilm containing one of no hydrogen and little hydrogen, and said firstand second films are films whose etching selective ratios are different.9. The production method according to claim 1, wherein said first filmis a film containing one of no hydrogen and little hydrogen, and saidfirst and second films are insulating films whose etching selectiveratios are different.
 10. A production method of a semiconductorintegrated circuit device having: a memory cell composed of a memorycell selecting n channel MISFET and a capacitor which are formed in amemory cell forming area of a semiconductor substrate; and an n channelMISFET and a p channel MISFET which are formed in a peripheral circuitforming area, said production method comprising: (a) a step of forming agate insulating film on said semiconductor substrate; (b) a gateelectrode forming step of forming a silicon film and an insulating filmon said gate insulating film, and forming, by patterning, gateelectrodes of a memory cell selecting n channel MISFET, an n channelMISFET, and a p channel MISFET and insulating films on the upperportions thereof, wherein said gate electrode forming step comprises thesteps of: introducing a p type impurity into a silicon film constitutingthe gate electrode of said memory cell selecting n channel MISFET andthe gate electrode of said p channel MISFET; and introducing an n typeimpurity into a silicon film constituting the gate electrode of said nchannel MISFET; (c) a step of depositing a first film on saidsemiconductor substrate, and removing said first film in the memory cellforming area; (d) a step of depositing a second film on saidsemiconductor substrate; (e) a step of performing an anisotropic etchingrelative to said first and second films in said peripheral circuitforming area, and thereby leaving the first and second films on asidewall of the gate electrode in said peripheral circuit forming area;and (f) a step of using said first and second films as a mask to implantan impurity into both sides of each of the gate electrodes of said nchannel MISFET and said p channel MISFET and thereby form asemiconductor area.
 11. The production method according to claim 10,further comprising a step of forming said capacitor connected to thememory cell selecting n channel MISFET, wherein said step of formingsaid capacitor includes a step of forming capacitors made of metal, fora lower electrode and an upper electrode thereof.
 12. The productionmethod according to claim 11, wherein metal composing one of said lowerelectrode and said upper electrode is Ru.
 13. The production methodaccording to claim 1, wherein the arrangement of said memory cell is anopen bit line arrangement.
 14. A semiconductor integrated circuit devicecomprising: a memory cell composed of a memory cell selecting n channelMISFET and a capacitor which are formed in a memory cell forming area ofa semiconductor substrate; and an n channel MISFET and a p channelMISFET which are formed in peripheral circuit forming areas, whereineach of said n channel MISFET and said p channel MISFET includes: asource and drain formed in said semiconductor substrate; a gateelectrode formed between said source and drain on the semiconductorsubstrate via a gate insulating film; and an insulating film formed onsaid gate electrode, said memory cell selecting n channel MISFETincludes: a source and drain formed in said semiconductor substrate; agate electrode formed between said source and drain on the semiconductorsubstrate via a gate insulating film; an insulating film formed on saidgate electrode; and a film formed on a sidewall of the gate electrode ofsaid memory cell selecting n channel MISFET, a p type impurity iscontained in the gate electrode of said memory cell selecting n channelMISFET and in the gate electrode of said p channel MISFET, and an n typeimpurity is contained in the gate electrode of said n channel MISFET,and the source and drain of each of said n channel MISFET and said pchannel MISFET is formed with using, as a mask, a film thicker than afilm formed on the sidewall of the gate electrode of said memory cellselecting n channel MISFET.
 15. The semiconductor integrated circuitdevice according to claim 14, wherein a conductive film is formedbetween the films formed on the sidewalls of said gate electrode and agate electrode adjacent thereto in said memory cell forming area and isformed on said source and drain.
 16. The semiconductor integratedcircuit device according to claim 14, wherein each of said insulatingfilm formed on said gate electrode and the film formed on the sidewallof the gate electrode of said memory cell selecting n channel MISFET isa film containing one of no hydrogen and little hydrogen.
 17. Thesemiconductor integrated circuit device according to claim 15, whereinthe film formed on the sidewall of the gate electrode of said memorycell selecting n channel MISFET is a silicon oxide film, and saidconductive film is a silicon film.
 18. The semiconductor integratedcircuit device according to claim 14, wherein said capacitor includes alower electrode and an upper electrode which are made of metal, and acapacitor insulating film.
 19. The semiconductor integrated circuitdevice according to claim 18, wherein metal composing one of said lowerelectrode and said upper electrode is Ru.
 20. The semiconductorintegrated circuit device according to claim 14, wherein the arrangementof said memory cell is an open bit line arrangement.
 21. A semiconductorintegrated circuit device having a memory cell composed of a memory cellselecting n channel MISFET and a capacitor, said semiconductorintegrated circuit device comprising: a source and drain formed in asemiconductor substrate; a gate electrode formed between said source anddrain on the semiconductor substrate through a gate insulating film, thegate electrode containing a p type impurity; and a first film formed onsaid gate electrode and a second film formed on a sidewall of said gateelectrode, wherein each of said first and second films is a filmcontaining one of no hydrogen and little hydrogen.
 22. The semiconductorintegrated circuit device according to claim 21, wherein a conductivefilm is formed between the films formed on the sidewalls of said gateelectrodes and a gate electrode adjacent thereto and is formed on saidsource and drain.